The present invention relates to integrated circuits which perform arithmetic operations and are controlled by a system clock.
Coprocessors and/or floating point units can perform a variety of arithmetical functions. Certain functions, such as addition, subtraction and logical operations could be implemented completely combinatorially. Other operations, such as double precision multiplication, division, and square root might often be implemented as a collection of combinatorial blocks separated by registers and/or latches. In general, all arithmetic functions could be implemented as one or more combinatorial circuit blocks (sometimes also called "sections" or "pipes"), each separated from other combinatorial blocks by storage elements (latches or registers). Each may be used zero, one or more times during a particular operation. Blocks could also be shared by several functions. For example, a large combinatorial circuit could often be shared among division, square root, and multiplication algorithms.
A completely combinatorial implementation of an algorithm (addition, for example), is the simplest of the above implementations: it has only one combinatorial block and no storage elements.
Each combinatorial block requires no less than a certain amount of time to generate a correct result after its operands appear in (are clocked into) its input storage elements. The control signal that clocks new operands into the block's input registers is often called a start signal for this block. The time allocation for each pipe (in order for it to produce a correct result) is implemented via a timer that counts a certain number of system clock cycles after the corresponding start signal. Each section could require one or more system clock cycles, depending on the system cycle time. In general, for a particular pipe with a particular set of inputs, the number of system cycles allowed for operation completion, multiplied by the cycle time, has to be greater than or equal to the minimum amount of time required for the correct result to be computed by the pipe.
Currently (in the present art), the number of cycles allowed for each pipe is hard-wired into the integrated circuit implementation. The number of cycles for a pipe cannot be changed via hardware means outside of the integrated circuit.
If the hard-wired number of cycles allowed for a certain pipe is too small, this particular pipe will become the limiting factor in determining the coprocessor's fastest cycle time. On the other hand, if the number of cycles for the same pipe is too big, the system will not be able to take full advantage of the pipe's speed.